1. Field of the Invention
This invention relates generally to wafer burn-in test circuits for semiconductor memory devices, and more parlicularly, to a wafer burn-in test circuit for sensing a cell failure in the wafer state.
2. Description of the Related Art
To guarantee the reliability of a semiconductor chip, a burl-in test is carried out after the wafer fabricating process is completed. Burn-in tests are generally performed after assembly when the chip is in a packaged state. Failed chips are discarded after the burn-in test is completed. However, this results in unnecessary expenditures of time and costs on assembling and testing failed chips.
Most failures in a dynamic random access memory (DRAM) are single-bit failures. Hence, in order to sense the failures, screening must be performed for a relatively long time. Single-bit failures are directly related to leakage current in imperfect memory cells. Leakage current is generated by failures in the transmission gate oxide layer, the capacitor dielectric layer, the storage node junction, etc.
In a conventional burn-in test implemented at the package state, the supply efficiency of a stress voltage supplied to the memory cell is very low because one word line is selected per thousands of cycles (for example, 4096 or 8192 cycles in a 64 Megabit DRAM). As the integration level of semiconductor memory devices increases, the supply efficiency of this stress voltage is reduced. In order to reduce burn-in test time and to improve the supply efficiency of the stress voltage, a method for simultaneously selecting all the word lines has been developed. By implementing this method at a wafer state, the yield is improved and production costs are reduced.
FIG. 1 is a block diagram illustrating a prior art semiconductor memory device having a sub word line driver. Referring to FIG. 1, memory cell arrays 101A and 101B include a plurality of unit memory cells. Word lines WL0-WL3 are connected to the memory cells and to corresponding sub word line drivers 102. A global word line enable signal NWE generated by a row decoder 103 is supplied to the sub word line driver 102 to activate the entire word lines WL0-WL3.
The basic operating principle of a wafer state burn-in test used with the prior art circuit of FIG. 1 will now be described. If an external wafer burn-in activation signal WBE, which indicates that the wafer burn-in mode has started, is applied to an additional test pad, control signals CON.sub.-- A and CON.sub.-- B are applied to the switching circuits of FIGS. 2A and 2B, respectively. The switching circuit of FIG. 2A consists of an NMOS transistor 201 having a channel connected between an input terminal to which a high voltage VPP is applied and a line WBEVSS.sub.-- 0 and having a gate connected to the control signal CON.sub.-- A, and a PMOS transistor 202 having a channel connected between a ground terminal and the line WBEVSS.sub.-- 0 and having a gate connected to the control signal CON.sub.-- A. The switching circuit of FIG. 2B consists of an NMOS transistor 203 having a channel connected between the input terminal to which the high voltage VPP is applied and a line WBEVSS.sub.-- E and having a gate connected to the control signal CON.sub.-- B, and a PMOS transistor 204 having a channel connected between the ground terminal and the line WBEVSS.sub.-- E and having a gate connected to the control signal CON.sub.-- B.
These switching circuits provide different signals depending on whether the device is in a normal mode of operation or a wafer burn-in test mode of operation. The control signals CON.sub.-- A and CON.sub.-- B can be selectively activated by the user and are received through the pad. For example, if the control signal CON.sub.-- A having a logic "HIGH" level is applied to the switching circuit, the high voltage signal VPP is applied to the odd word lines WL1 and WL3 through the line WBEVSS.sub.-- 0. All of the word lines WL1 and WL3 which correspond to sub word line drivers 102 which use the same line WBEVSS.sub.-- 0 receive the VPP signal.
If the control signal CON.sub.-- B is activated, the high voltage signal VPP is supplied to the sub word line drivers 102 through the line WBEVSS.sub.-- E to operate the word lines WL0 and WL2. Therefore, the memory cells connected to the word lines WL0 and WL2 are turned on to read or write data. If both of the control signals CON.sub.-- A and CON.sub.-- B are simultaneously operated, all of the memory cells connected to the word lines WL0-WL3 are turned on.
Data is written into the memory cell connected to the word line activated by the above-described operation through an additional data line. The circuit of FIG. 1 has a data pattern as shown in FIG. 7A after data is written into the memory cells.
FIG. 3 is a block diagram of another prior art semiconductor memory device showing the connection relationship between the sub word line drivers and the word lines. FIG. 3 is similar to FIG. 1. However, the sub word line driver 102 connected to a line WBEVSS.sub.-- T is coupled to the word lines WL1 and WL2, and the sub word line driver 102 connected to a line WBEVSS.sub.-- C is coupled to the word lines WL0 and WL3.
Switching circuits for supplying the high voltage signal VPP to the lines WBEVSS.sub.-- T and WBEVSS.sub.-- C shown in FIG. 3 are illustrated in FIGS. 4A and 4B. The switching circuit of FIG. 4A consists of an NMOS transistor 401 having a channel connected between the input terminal to which the high voltage VPP is applied and the line WBEVSS.sub.-- T and having a gate connected to the control signal CON.sub.-- A, and a PMOS transistor 402 having a channel connected between the ground terminal and the line WBEVSS.sub.-- T and having a gate connected to the control signal CON.sub.-- A. The switching circuit of FIG. 4B has the same configuration as that of FIG. 4A except that it is controlled by the control signal CON.sub.-- B instead of CON.sub.-- A.
The circuit of FIG. 3 has a data pattern as shown in FIG. 7B after data is written into the memory cells.
FIG. 5 illustrates a prior art global word line driving circuit which the global word line enable signal NWE for activating the word lines WL0-WL3. The circuit of FIG. 5 drives the signal NWE to a logic "LOW" level in response to a signal PDPXi, which is enabled when a row address strobe signal /RAS is deactivated to a logic "HIGH" level. The circuit of FIG. 5 drives the global word line enable signal NWE to a logic "HIGH" level when a row decoding signal RAi is activated. The global word line enable signal NWE is a signal
The global word line driving circuit of FIG. 5 includes a PMOS transistor 501 having a channel connected between a power voltage VCC and a node N1 and having a gate connected to the signal PDPXi, a PMOS transistor 502 having a channel connected between the power voltage VCC and the node N1, an inventer 504 connected between the node N1 and the global word line enable signal NWE, and an NMOS transistor 503 having a channel connected between the node N1 and the ground terminal and having a gate connected to the row decoding signal RAi.
FIG. 6 illustrates the sub word line driver 102 of FIGS. 1 and 3. The sub word line driver includes an NMOS transistor 602 having a channel connected between the global word line enable signal NWE and a node N2 and having a gate connected to a word line activation signal PXiD.sub.-- i, an NMOS transistor 603 having a channel connected between a signal PXiD.sub.-- P and the node N2, an NMOS transistor 601 having a channel connected between a gate of the NOS transistor 603 and the global word line enable signal NWE and having a gate connected to the power voltage VCC, and an NMOS transistor 604 having a channel connected between the node N2 and a line WBEVSS and having a gate connected to a signal /PXi.
When forming the data pattern shown in FIG. 7A through the above circuits, one type of data can be written to a selected memory cell, while the opposite data can be written to the memory cell adjacent the selected memory cell. Therefore, the chip can be tested for its ability to withstand stress between the adjacent memory cells.
However, a problem with the circuit of FIG. 1 is that, when the data pattern of FIG. 7A is formed, the ability to withstand bit line stress generated by a sensing operation can not be tested because the written data form can not perform the sensing operation. That is, since the opposite data is written in a pair of the same bit lines BL and /BL, it is difficult to determine whether there is a failure.
A problem with the circuit of FIG. 3 is that, when forming the data pattern shown in FIG. 7B, some of the data written in adjacent memory cells are opposite to each other, and some of data is the same. Hence, the chip can not be tested for its ability to withstand stress between the adjacent memory cells that have the same data in adjacent memory cells. That is, since the same data is written on the word lines WL1 and WL2, the stress between adjacent memory cells can not be tested. In this structure, it is difficult to perform the various stress tests for reliability.
Another problem with the prior art is that, in the sub word line drivel of FIG. 6, in order to obtain a sufficient word line activation level, the high voltage VPP is applied through the line WBEVSS to the word line WL by operation of the NMOS transistor 604. Therefore, the signal /PXi, which is applied to the gate of NMOS transistor 604, should be higher than the high voltage VPP. This, however, tends to cause break down in the NMOS transistor 604.
Accordingly, a need remains for a technique for a method and apparatus which overcomes the above mentioned problems when performing a wafer burn-in test on a semiconductor memory device